Lateral bipolar transistor

ABSTRACT

A substantially concentric lateral bipolar transistor and the method of forming same. A base region is disposed about a periphery of an emitter region, and a collector region is disposed about a periphery of the base region to form the concentric lateral bipolar transistor of the invention. A gate overlies the substrate and at least a portion of the base region. At least one electrical contact is formed connecting the base and the gate, although a plurality of contacts may be formed. A further bipolar transistor is formed according to the following method of the invention. A base region is formed in a substrate and a gate region is formed overlying at least a portion of the base region. Emitter and collector terminals are formed on opposed sides of the base region. The gate is used as a mask during first and second ion implants. During the first ion implant the ions bombard the substrate from a first direction to grade a base/emitter junction, and during the second ion implant ions bombard the substrate from a second direction to grade a base/collector junction. Also a lateral bipolar transistor having a decreased base width as a result of implanting ions after fabrication of collector and emitter regions to enlarge the collector and emitter regions, thereby decreasing the base region and increasing gain.

This application is a Continuation of U.S. application Ser. No.09/233,871 filed Jan. 20, 1999, now U.S. Pat. No. 6,166,426 which is aDivisional of U.S. application Ser. No. 09/026,235 filed Feb. 19, 1998,now U.S. Pat. No. 5,965,923, which is a Divisional of U.S. applicationSer. No. 08/766,659 filed Dec. 16, 1996, now U.S. Pat. No. 5,945,726.

FIELD OF THE INVENTION

The invention relates to semiconductor technology, and in particular toa lateral bipolar transistor and the process for making same.

BACKGROUND OF THE INVENTION

Recently respectable bipolar transistors have been formed using a CMOS(complementary metal-oxide semiconductor) transistor in a typical CMOSprocess. These bipolar transistors are also referred to as lateralbipolar transistors and are reported to have a threshold frequency (t)as high as 3.7 Ghz and a Beta as high as 1000. This alternate method offorming a bipolar transistor has some strong advantages. The process isextremely simple compared to a typical BiCMOS process that usescomplicated and expensive process flows costing 30-40% more than atypical CMOS flow. The use of a CMOS flow to create a lateral bipolartransistor adds negligible cost to a current CMOS process and provides acapable bipolar transistor.

The lateral bipolar transistor is fabricated using a typical lightlydoped drain (LDD) MOS transistor. An NPN device is formed from an NMOStransistor and a PNP device is formed from a PMOS transistor. The basewidth of the lateral bipolar transistor is determined by and is usuallyequal to the MOS channel length. As MOS devices have shrunk the channellengths have approached the base width of a bipolar making the lateralbipolar transistor possible.

In one variation a base implant is added to the process steps to balancethe bipolar and MOS modes of operation. In addition the typical lateralbipolar transistor employs a base-gate contact for providing anelectrical connection between the base and gate of the lateral bipolartransistors. Since the base is typically fabricated in the well, thegate depletes the base while the substrate contact controls the basevoltage.

The Inventors have discovered that the lateral bipolar transistors,fabricated according to the structures described above, have a reductionin gain at high currents or at high bias voltages. Thus, it would bedesirable to have a CMOS-based bipolar transistor having improvedbipolar performance during high current or high bias voltage conditions.

SUMMARY OF THE INVENTION

One exemplary embodiment of the invention is a substantially concentriclateral bipolar transistor and the method of forming same. The lateralbipolar transistor includes a base region disposed about a periphery ofan emitter region and a collector region disposed about a periphery ofthe base region. A gate overlies the substrate and at least a portion ofthe base region. At least one electrical contact is formed connectingthe base and the gate, although a plurality of contacts may be formed.The invention includes a metal oxide semiconductor inversion regionformed in the substrate and a retrograde well formed below the inversionregion.

In a further exemplary embodiment a bipolar transistor is formedaccording to the following method. A base region is formed in asubstrate and a gate region is formed overlying at least a portion ofthe base region. Emitter and collector terminals are formed on opposedsides of the base region. The gate is used as a mask during first andsecond ion implants. During the first ion implant the ions bombard thesubstrate from a first direction to grade a base/emitter junction, andduring the second ion implant ions bombard the substrate from a seconddirection to grade a base/collector junction.

In a further exemplary embodiment the invention is a lateral bipolartransistor having a decreased base width. The decreased base region iscreated by implanting ions after fabrication of collector and emitterregions to enlarge the collector and emitter regions, thereby decreasingthe base region and increasing gain.

BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a top planar view of a layout of the substantially concentriclateral bipolar transistor of the invention.

FIG. 2 is a cross sectional view of the transistor in FIG. 1, takenalong line 2—2 of FIG. 1, following a high energy, high dose implant.

FIG. 3 is a top planar view of a lateral bipolar transistor of a furtherembodiment of the invention.

FIG. 4 is a cross sectional view of the bipolar transistor of FIG. 3,taken along line 4—4 of FIG. 3.

FIG. 5 is a cross sectional view of one type of base-gate contact.

FIGS. 6-13 are cross sectional views of a process for forming thelateral bipolar transistor of the invention.

FIG. 14 is a block schematic of a memory system of the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

One embodiment of the present invention is a concentric lateral bipolartransistor and the method of forming same. The invention includesmultiple base-gate contacts. FIG. 1 is a top planar view of a layout ofthe concentric lateral bipolar transistor 1 of the present invention.This particular layout advantageously reduces the consumption of diearea by the lateral bipolar transistor while enhancing performance ofthe lateral bipolar transistor 1. The base region underlies a poly gateregion 3 and is essentially a three dimensional annulus of any shapeinterposed between an emitter region 5 and a collector region 10. Thus,the base region is disposed about the emitter region 5 (represented hereas a polygonal structure), and the collector region 10 is disposed aboutthe base region. A reduced base resistance and/or reduced straycapacitance of the concentric lateral bipolar transistor 1 improves theFt. In this configuration all of the emitter current is driven towardthe collector thereby increasing collector efficiency. In FIG. 1 twobase-gate contacts 15 are used to reduce the base resistance. Eventhough there are two base-gate contacts 15 the total base contact areais very small thereby contributing to minimum device size. In thisparticular layout of the bipolar transistor 1, an additional, masked,high energy, high dose, angled implant is used to selectively increase asize of the emitter and collector junctions thereby reducing the basewidth and providing higher gain and higher Ft.

FIG. 2 is a cross sectional view of the transistor in FIG. 1 followingthe high energy, high dose implant 20.

FIG. 3 is a top planar view of the lateral bipolar transistor 25 of afurther embodiment of the present invention, and FIG. 4 is a crosssectional view of the bipolar transistor 25 of FIG. 3. The lateralbipolar transistor 25 is linear. As shown in FIG. 4, a first angledimplant 26 grades the base doping at the base-emitter junction, and asecond angled implant 27 grades the base at the base-collector junction.The graded base 28 at the base-emitter junction increases the driftvelocity of minority carriers while the graded base 29 at thebase-collector junction increases the doping of the collector region 30which improves the high current operation of the transistor. These twoimplants use opposite dopant types. Therefore the linear layout is usedin order to identically orient the collector region 30 and the emitterregion 35 such that only one masking step is required to protect otherdevices during the angled implant of the lateral bipolar transistor 25.Since only a small number of bipolar devices are needed in mostapplications, such as sense amplifiers and output drivers, it ispossible to orient the emitter region 35 and collector region 30 whenusing the linear arrangement of the invention in order that the angledimplants do not have to be masked separately. Since each of theseimplants is done at an angle, the poly gate 40 shields the oppositeelectrode so that the one implant does not affect the other. The highenergy, high dose angle implant of the first embodiment can also be usedin this embodiment, without the addition of a further mask, to increasethe depths of the emitter region 35 and the collector region 30 anddecrease the base width.

In both embodiments described above, the base resistance of the bipolartransistors is further reduced by adding retrograde wells. In essence,the doping of is the wells below the MOS inversion regions is increasedto reduce the base resistance without affecting the critical surfacedoping. Both NPN and PNP bipolar transistors are formed on either N or Ptype substrates with proper well formation and biasing.

In addition, in both embodiments described above a base-gate contact isformed. In most cases a single buried contact reduces the die areaconsumed. FIG. 5 illustrates a cross sectional view of an exemplary typeof base-gate contact 45 which can be formed according to the presentinvention. When forming the gate a first poly layer 50 is deposited andetched to expose the base 55 in the contact region. A second poly layer60 is then deposited to contact the base 55. Both poly layers 50 and 60are patterned and etched to define the gate region. A thick oxide layer65 is deposited to overly the poly layers 50 and 60. The oxide 65 ispatterned and etched to create an opening exposing the poly layer 60.Tungsten is then formed in the opening. The tungsten forms the basetgatecontact 45. Although only one type of base-gate contact is shown in FIG.5 other types may also be used. In addition a plurality of the base-gatecontacts (shown in FIG. 5) may be used in the bipolar transistor of theinvention, for example, it may be used to form the base-gate contacts 15used in the bipolar transistor shown in FIG. 1.

The process for making an NPN lateral bipolar transistor of theinvention is shown cross sectionally in FIGS. 6-13. The cross section isrepresentative of the cross section indicated in FIG. 1. The particularprocess described below is for an N type substrate. It is understoodthat a similar process is used to form the transistors of the inventionwith a P type substrate.

As illustrated in FIG. 6 a light, 2E¹², phosphorus implant preferably inthe range of about 50 KeV is performed to adjust a surface concentrationof the N-type substrate 100 and to form N-wells 105. A thick oxide 110is then deposited and photolithography is used to pattern the thickoxide 110 to define a future P-well opening. Boron is implanted inexposed regions preferably at a dose of 7E¹² at 50 KeV and is diffusedpreferably to a depth of 3 micro. Next a high energy boron implantpreferably of 2E¹³ at 600 KeV forms a retrograde P-well 112 whichreduces the base resistance in the bipolar transistors and improveslatch-up immunity. The thick oxide layer is then removed during an etch.

As, shown in FIG. 7 an oxide pad 115 (preferably about 200 Angstromthick) is grown and a nitride layer 120 (preferably about 2000 Angstromthick) is deposited and patterned with a photoresist mask 125.

In FIG. 8 the nitride 120 is etched in unmasked regions to expose thesubstrate. A field oxide region 130 (preferably about 450 Angstromthick) is then grown on the exposed portion of the substrate. Next theoxide pad 115 and the nitride layer 120 are removed.

FIG. 9 shows a sacrificial oxide layer 140 which is preferentially grownto about a 350 Angstrom thickness. A photoresist mask 145 defines fieldimplant regions. A first boron implant of preferably) about 3E¹² atabout 130 KeV and a second enhancement boron implant of (preferably) atabout 2E¹² at about 25 KeV are performed to form P type field implantregions 150. The photoresist mask 145 is then removed and thesacrificial oxide 140 is striped. An optional base implant of(preferably) about 1.0E¹³ cm-2 of boron difluoride ions at 20 KeV mayalso be implanted to guide the electrons away from the surface of theintrinsic base.

As shown in FIG. 10, a gate oxide layer 155 is grown preferably to athickness of 100 Angstroms. In this first embodiment a firstpolycrystalline silicon layer 160 having a thickness of 500 Angstroms isdeposited and then patterned and etched according to a photoresist mask(not shown) to define contact regions to the substrate. The unmaskedfirst polycrystalline silicon layer 160 and the gate oxide layer 155 arethen etched to expose the substrate in the contact regions which are notshown in this cross section. Next, a second polycrystalline siliconlayer 165, preferably of about 1500 Angstroms in thickness, is depositedoverlying the first polysilicon layer 160. A Boron implant preferably ofabout 1E¹⁵ at 25 KeV is performed to dope the polycrystalline siliconlayers 160 and 165. This implant is followed by a deposition of an oxidelayer 170, preferably having a thickness of about 2500 Angstroms.Finally gates are defined with photoresist mask 175.

The oxide layer 175, the polycrystalline silicon layers 165 and 160, andgate oxide layer 155 of FIG. 10 are etched to form gate regions 180shown in FIG. 11. A lightly doped drain Arsenic implant, having apreferred dosage of 1E¹² at 100 KeV and an angled Arsenic implant havinga preferred dosage of 5E¹² at 100 KeV are performed to form N+ emitterregion 185, N+ collector region 190 in the lateral bipolar transistor195 and to form source/drain regions 196 in the CMOS 200. As shown inFIG. 11 and the top planar view in FIG. 1, the base 201 (underlying thepoly gate region of FIG. 1) is concentric with the annular shapedcollector 190 (collector 10 of FIG. 1) and lies in between the collector190 and the emitter 185 (emitter 5 of FIG. 1).

As shown in FIG. 12, the gate regions 180 of the lateral bipolartransistor 195 are used as a pattern during a bipolar implant. Otherdevices such as CMOS device 200 are masked with photoresist 205 duringthis step. The bipolar implant deepens and widens the collector region190 and emitter region 185 thereby decreasing the width of the base 201in the lateral bipolar transistor 195. The bipolar implant uses a dosageof arsenic atoms preferably ranging between about 5E¹⁴ and about 1E¹⁶(most preferably at 5E¹⁵) and at an energy of about 30 to about 200 KeV(most preferably 120 at KeV). The bipolar implant is preferablyperformed at an angle of 20 degrees from a perpendicular to thesubstrate, although the angle may range between about 10 and about 40degrees.

As seen in FIG. 13, the photoresist 205 of FIG. 12 is removed and aconformal oxide layer (not shown) is deposited and then etched to formspacers 215 on the sidewalls of the gate regions 180. Following thespacer 215 formation an arsenic implant is performed preferably at adose of 3E15 at 50 KeV at zero degrees thereby patterning N+ source 225and drain 230 regions in the CMOS device 200.

The bipolar transistors 1, 25, and 195 of the invention, shown in FIGS.1, 3 and 11-13 respectively, of the invention are typically used in amonolithic memory device 300, such as a dynamic random access memorydevice, as shown in FIG. 14. The monolithic memory device 300 and aprocessor 305 form part of a memory system 310. The processor 305 istypically used to generate external control signals which access themonolithic memory device 300 either directly or through a memorycontroller.

Although exemplary embodiments have been described above the inventionshould only be limited by the claims.

What is claimed is:
 1. A lateral bipolar transistor, comprising: anemitter region; a collector region surrounding, and laterally displacedfrom, the emitter region; a device base region, comprising: a first baseregion interposed between the emitter region and the collector region,the base region having a first base region width; a tailored base regionadjacent to the first base region that modifies the first base regionwidth; and a gate region overlying at least a portion of the device baseregion, wherein the gate region is in electrical communication with thedevice base region.
 2. The lateral bipolar transistor of claim 1,wherein the tailored base region comprises: an emitter graded regionadjacent to a base-emitter junction; and a collector graded regionadjacent to a base-collector junction.
 3. A system comprising: aprocessor; and a memory device in communication with the processor,wherein the memory device comprises a lateral bipolar transistor,further wherein the lateral bipolar transistor comprises: an emitterregion; a collector region surrounding, and laterally displaced from,the emitter region; a device base region, comprising: a first baseregion interposed between the emitter region and the collector region,the base region having a first base region width; a tailored base regionadjacent to the first base region that modifies the first base regionwidth; and a gate region overlying at least a portion of the device baseregion, wherein the gate region is in electrical communication with thedevice base region.
 4. The lateral bipolar transistor of claim 3,wherein the tailored base region comprises: an emitter graded regionadjacent to a base-emitter junction; and a collector graded regionadjacent to a base-collector junction.
 5. A lateral bipolar transistor,comprising: an emitter region, wherein the emitter region has a firstdopant type a collector region laterally displaced from the emitterregion, wherein the collector region has a second dopant type, furtherwherein the second dopant type is opposite the first dopant type; a baseregion interposed between the emitter region and the collector region,wherein an interface between the base region and the emitter regionforms a base-emitter junction, further wherein an interface between thebase region and the collector region forms a base-collector junction; agate region overlying at least a portion of the base region, wherein thegate region is in electrical communication with the base region; anemitter graded region adjacent to the base-emitter junction; and acollector graded region adjacent to the base-collector junction.
 6. Asystem comprising: a processor; and a memory device in communicationwith the processor, wherein the memory device comprises a lateralbipolar transistor, further wherein the lateral bipolar transistorcomprises: an emitter region, wherein the emitter region has a firstdopant type a collector region laterally displaced from the emitterregion, wherein the collector region has a second dopant type, furtherwherein the second dopant type is opposite the first dopant type; a baseregion interposed between the emitter region and the collector region,wherein an interface between the base region and the emitter regionforms a base-emitter junction, further wherein an interface between thebase region and the collector region forms a base-collector junction;and a gate region overlying at least a portion of the base region,wherein the gate region is in electrical communication with the baseregion; an emitter graded region adjacent to the base-emitter junction;and a collector graded region adjacent to the base-collector junction.7. A lateral bipolar transistor, comprising: an N+-type emitter regionformed in a P-well; an N+-type collector region formed in the P-wellsurrounding, and laterally displaced from, the emitter region; a P-typebase region, comprising: a first base region interposed between theemitter region and the collector region in the P-well, the base regionhaving a first base region width; a tailored base region adjacent to thefirst base region that modifies the first base region width; and a gateregion overlying at least a portion of the P-type base region, whereinthe gate region is in electrical communication with the P-type baseregion.
 8. The lateral bipolar transistor of claim 7, wherein thetailored base region comprises: an emitter graded region adjacent to abase-emitter junction; and a collector graded region adjacent to abase-collector junction.
 9. A lateral bipolar transistor, comprising: aP+-type emitter region formed in an N-well; a P+-type collector regionformed in the N-well surrounding, and laterally displaced from, theemitter region; an N-type base region, comprising: a first base regioninterposed between the emitter region and the collector region in theN-well, the base region having a first base region width; a tailoredbase region adjacent to the first base region that modifies the firstbase region width; and a gate region overlying at least a portion of theN-type base region, wherein the gate region is in electricalcommunication with the N-type base region.
 10. The lateral bipolartransistor of claim 9, wherein the tailored base region comprises: anemitter graded region adjacent to a base-emitter junction; and acollector graded region adjacent to a base-collector junction.
 11. Asystem comprising: a processor; and a memory device in communicationwith the processor, wherein the memory device comprises a lateralbipolar transistor, further wherein the lateral bipolar transistorcomprises: an N+-type emitter region formed in a P-well; an N+-typecollector region formed in the P-well surrounding, and laterallydisplaced from, the emitter region; a P-type base region, comprising: afirst base region interposed between the emitter region and thecollector region in the P-well, the base region having a first baseregion width; a tailored base region adjacent to the first base regionthat modifies the first base region width; and a gate region overlyingat least a portion of the P-type base region, wherein the gate region isin electrical communication with the P-type base region.
 12. The systemof claim 11, wherein the tailored base region comprises: an emittergraded region adjacent to a base-emitter junction; and a collectorgraded region adjacent to a base-collector junction.
 13. A systemcomprising: a processor; and a memory device in communication with theprocessor, wherein the memory device comprises a lateral bipolartransistor, further wherein the lateral bipolar transistor comprises: aP+-type emitter region formed in an N-well; a P+-type collector regionformed in the N-well surrounding, and laterally displaced from, theemitter region; an N-type base region, comprising: a first base regioninterposed between the emitter region and the collector region in theN-well, the base region having a first base region width; a tailoredbase region adjacent to the first base region that modifies the firstbase region width; and a gate region overlying at least a portion of theN-type base region, wherein the gate region is in electricalcommunication with the N-type base region.
 14. The system of claim 13,wherein the tailored base region comprises: an emitter graded regionadjacent to a base-emitter junction; and a collector graded regionadjacent to a base-collector junction.
 15. The lateral bipolartransistor of claim 1, wherein the gate region is coupled to the devicebase region through a base-gate contact.
 16. The lateral bipolartransistor of claim 1, wherein the tailored base region narrows thefirst base region width.
 17. The lateral bipolar transistor of claim 1,wherein the emitter graded region is doped oppositely from the collectorgraded region.
 18. The lateral bipolar transistor of claim 1, whereingate region includes a polysilicon gate region.
 19. The system of claim3, wherein the gate region is coupled to the device base region througha base-gate contact.
 20. The system of claim 3, wherein the tailoredbase region narrows the first base region width.
 21. The system of claim4, wherein the emitter graded region is doped oppositely from thecollector graded region.
 22. The system of claim 3, wherein gate regionincludes a polysilicon gate region.
 23. The system of claim 6, whereinthe gate region is coupled to the device base region through a pluralityof base-gate contacts.
 24. The system of claim 6, wherein the tailoredbase region narrows the first base region width.
 25. The system of claim6, wherein the emitter graded region is doped oppositely from thecollector graded region.